Field of Invention
The present invention belongs to the technical field of analog or digital-to-analog hybrid integrated circuit, and relates to a high-speed low-power-consumption trigger.
Description of Related Arts
A trigger, as an important sequential circuit structure, is widely applied to digital, analog and analog-to-digital hybrid integrated circuit. In recent years, with the continuous development of the manufacturing technology of the integrated circuit, the demand for a high-speed low-power-consumption trigger is gradually increasing. In order to adapt to the requirement of low-power, the supply voltage further reduces. Against to this trend, in order to ensure the operating performance of the trigger, some high-speed low-power-consumption trigger structures have been developed, including a SAFF (sense amplifier based trigger) structure, a MSAFF (modified sense amplifier based trigger) structure and a SBFF (self-blocking trigger) structure. The foregoing three structures have respective advantages and disadvantages thereof, but the foregoing three structures are quite difficult to simultaneously meet features: a simple structure, and an implementation of the high-speed low-power-consumption trigger.
To describe the foregoing problem in more details, operating principles and advantages and disadvantages of the foregoing three triggers are analyzed first.
FIG. 1 shows a trigger of SAFF structure. The trigger of SAFF structure comprises latches of two stages. A first-stage latch comprises NMOS transistors M0 to M3 and PMOS transistors M4 to M9, wherein a source electrode of M0 is grounded, a drain electrode of M0 is connected to source electrodes of M1 and M2, a gate electrode of M0 is connected to a clock signal CLK, a gate electrode of M3 is connected to a power source vdd, a source electrode and a drain electrode of M3 are connected to drain electrodes of M1 and M2, at the same time, the drain electrodes of M1 and M2 are connected to source electrodes of M4 and M5, gate electrodes of M1 and M2 are connected to an input signal D and a phase-inverted signal DB thereof, the transistor M3 is open all the time, and serves as a resistor to prevent a heavy voltage fluctuation from being generated at two ends of the transistor M3, M4/M5/M6/M7 constitute an input/output connected latch structure, M8 and M9 serve as enabling transistors and connect the power source vdd and output of the first-stage latch, and gate electrodes of M8 and M9 are connected to the clock signal CLK. A second-stage latch comprises NMOS transistors M10 to M13 and PMOS transistors M14 to M17, wherein source electrodes of M10 and M11 are grounded, drain electrodes of M10 and M11 are connected to source electrodes of M12 and M13 respectively, gate electrodes of M10 and M11 are connected to output signals SB and RB of the first-stage latch respectively, M12/M13/M14/M17 constitute an input/output connected latch structure, M15 and M16 serve as enabling transistors and connect the power source vdd and output of the second-stage latch, and gate electrodes of M15 and M16 are connected to the output SB and RB of the first-stage latch. When the clock signal CLK is a low electrical level, M0 is turned off, M8 and M9 are turned on, the first-stage latch is in a reset state, the output SB and RB of the first-stage latch are both high electrical levels, the second-stage latch is in a latching state, and output Q and QB of the second-stage latch maintain values in last state. When the clock signal CLK changes from the low electrical level to a high electrical level, M0 is turned on, M8 and M9 are turned off, the first-stage latch is flipped based on the input signal D and the phase-inverted signal DB thereof, one of the output signals SB and RB is a high electrical level, and the other is a low electrical level, and the output Q and QB of the second-stage latch are refreshed once. FIG. 2 is a diagram of an operating sequence of the trigger of SAFF structure. A delay time td1 between a rising edge of the clock CLK and data refreshing is a delay time of the trigger in FIG. 1, and the delay time is a sum of delay times of the two stages of latches. An advantage of FIG. 1 is that each stage of latch structure is relatively simple so that circuit design is quite easy to be implemented, but a disadvantage is that the two-stage latch structure is relatively slow, and the second-stage latch is also relatively slow.
FIG. 3 shows a trigger of MSAFF structure, as shown in FIG. 3, the trigger of SAFF structure comprises latches of two stages. A principle diagram of a first-stage latch thereof is the same as FIG. 1, and an operating principle thereof is also the same as that in FIG. 1. A second-stage latch comprises phase inverters I1 and I2, NMOS transistors M10/M11/M12/M16/M17/M18 and PMOS transistors M13/M14/M15/M19/M20/M21. The output SB/RB of the first-stage latch serve as input signals of the second-stage latch, input ends of the phase inverters I1 and I2 are connected to RB and SB respectively, output ends of the phase inverters I1 and I2 are connected to gate electrodes of M10 and M17, source electrodes of M10 and M17 are grounded, drain electrodes of M10 and M17 are connected to drain electrodes of M14 and M21 respectively, and connected to drain electrodes of M13/M12 and gate electrodes of M16/M20, and drain electrodes of M18/M19 and gate electrodes of M11/M15, source electrodes of M11 and M16 are grounded, drain electrodes of M11 and M16 are connected to source electrodes of M12 and M18, source electrodes of M15 and M20 are connected to a power source vdd, drain electrodes of M15 and M20 are connected to drain electrodes of M13 and M19, gate electrodes of M12 and M14 are connected to SB, gate electrodes of M18 and M21 are connected to RB, a gate electrode of M13 are connected to R, and a gate electrode of M19 are connected to S. When a clock signal CLK is a low electrical level, M0 is turned off, M8 and M9 are turned on, the first-stage latch is in a reset state, the output signals SB and RB of the first-stage latch are both high electrical levels, in the second-stage latch, M10/M17/M14/M21 are turned off, M12/M13/M18/M19 are turned on, and the second-stage latch is in a latching state. When the clock signal CLK changes from the low electrical level to a high electrical level, M0 is turned on, M8 and M9 are turned off, the first-stage latch is flipped based on an input signal D and DB, one of the output signals SB and RB is a high electrical level, and the other is a low electrical level, and the output Q and QB of the second-stage latch are refreshed once. FIG. 4 is a diagram of an operating sequence of the trigger of MSAFF structure. A delay time td2 between a rising edge of the clock CLK and data refreshing is a delay time of the trigger in FIG. 2, and the delay time is also a sum of delay times of the two stages of latches. Compared with FIG. 1, the second-stage trigger in FIG. 2 additionally comprises a pulling up/down path comprising M10, M14, M17, and M21, so that the second-stage latch in FIG. 2 is faster than the second-stage latch of structure [1]. An advantage of FIG. 2 is that the speed of the second-stage latch is relatively fast, but the structure is relatively complex and power consumption is relatively large, and the two-stage latch structure is relatively slow.
FIG. 5 shows a trigger of SBFF structure, as shown in FIG. 5, the trigger of SBFF structure comprises a control signal generation circuit and a latch of one stage, wherein NMOS transistors M0 to M4 and PMOS transistor M5 constitute the control signal generation circuit, NMOS transistors M6 to M11 and PMOS transistors M12 to M16 constitute the latch. A source electrode of M0 is grounded, a drain electrode of M0 is connected to source electrodes of M1 and M2, drain electrodes of M1 and M2 are connected to source electrodes of M3 and M4 respectively, drain electrodes of M3 and M4 are connected to a drain electrode of M5, a source electrode of M5 is connected to a power source vdd, gate electrodes of M0 and M5 are connected to a clock signal CLK, a gate electrode of M1 is connected to an output signal Q, a gate electrode of M3 is connected to an input signal D, a gate electrode of M2 is connected to a phase-inverted signal QB of the output signal Q, and a gate electrode of M4 is connected to a phase-inverted signal DB of the input signal D. In the latch, a source electrode of M10 is grounded, a drain electrode of M10 is connected to a source electrode of M11, a drain electrode of M11 is connected to source electrodes of M7 and M8, and serves as an output end of the trigger, M6/M9/M12/M13 constitute an input/output connected latch structure, output of M6/M9/M12/M13 also serves as output ends of the latch, a gate electrode of M16 is grounded, drain electrodes of M12 and M13 are connected to two ends of M16, and are connected to drain electrodes of M14 and M15, source electrodes of M14 and M15 are connected to the power source vdd, gate electrodes of M10 and M11 are connected to a control signal X and the clock signal CLK respectively, gate electrodes of M8 and M14 are connected to the input signal D, gate electrodes of M7 and M15 are connected to the phase-inverted signal DB of the input signal D. When the clock signal CLK is a low electrical level, the control signal X is a high electrical level, and the latch is in a latching state. When the clock signal CLK changes from the low electrical level to a high electrical level, and if the input signal D in this state and the output signal Q in last state are both high electrical levels or both low electrical levels, the control signal X becomes a low electrical level, and the latch still maintains the last state. A sequence diagram thereof is shown in FIG. 6(a), otherwise the control signal X maintains the high electrical level. In the latch, M10 and M11 are simultaneously turned on, the output signal Q of the latch is flipped, and a sequence diagram thereof is shown in FIG. 6(b). An advantage of FIG. 5 is that the structure of the trigger comprises a control signal generation circuit and a latch of one stage, and the trigger additionally comprises a pulling down path comprising M7 and M8. Therefore, the speed of the trigger is increased compared with structures in FIG. 1 and FIG. 3. However, the control signal generation circuit and an enabling transistor of the latch are formed by NMOS transistors connected in series, on-resistance is relatively large, parasitic capacitance at an output end of the trigger is also relatively large, and therefore, the trigger is not applicable to design for a high-speed circuit.